Hi, I'm Maxime!
I'm a post-doctoral fellow at INRIA Bordeaux, part of the TADAAM team. I work on scheduling, data locality, GPUs and energy-aware computing. I hope to make HPC systems and Cloud computing run fast, green and while using fewer computing resources. KeyWords: Scheduling, Data Locality, GPUs, Energy/Carbon-Aware Scheduling, HPC Users Incentives, Erasure Coding, Parallel Algorithms, Deadline-Aware Scheduling, LLM scheduling, IO clustering, Data Intensive Computing
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About
- Before working at INRIA Bordeaux, I was a post-doctoral fellow at the University of Chicago and Argonne Nationnal Lab. I was part of Globus Labs and worked with the supervision of Ian Foster and Kyle Chard.
- I received my PhD at ENS Lyon in 2023. I worked in the ROMA team at the LIP laboratory under the supervision of Loris Marchal (ENS Lyon, CNRS) and in the STORM team at INRIA Bordeaux under the supervision of Samuel Thibault (Université de Bordeaux, Inria).
Selected publications
Core Hours and Carbon Credits: Incentivizing Sustainability in HPC
SC 2025
User choices, such as where to run, can be as consequential as provider decisions for the environmental impact of HPC. Our survey of 300 HPC users finds that fewer than 30% of them are aware of their energy consumption. We propose two multi-resource accounting methods that charge for computations based on their energy consumption or carbon footprint, and evaluate them through simulation and a user study. Feedback alone had no effect, but associating energy with cost incentivized users to select more efficient resources and use 40% less energy.
A scheduler to foster data locality for GPU and out-of-core task-based linear algebra applications
JPDC 2025 (extended work) - IPDPS 2022 (orginal work)
We propose a scheduler for task-based runtimes that improves data locality for out-of-core linear algebra computations in order to reduce data movement, with a data-aware strategy for both task scheduling and data eviction from limited memories. Implemented in StarPU, it achieves comparable performance to existing schedulers when memory is not a constraint, and significantly better performance when application input data exceeds memory, on both GPUs and CPU cores. The proposed scheduler is available on the main branch of StarPU and will be realesed with StarPU 1.5. You can use it right now by selecting the "darts" scheduler.
D-Rex: Heterogeneity-Aware Reliability Framework and Adaptive Algorithms for Distributed Storage
ICS 2025
Distributed storage is challenged by the heterogeneity of nodes in capacity, I/O performance, and failure rates, while erasure coding adds reliability at a high computational cost. D-Rex tackles both: we propose two dynamic schedulers, D-Rex LB and D-Rex SC, that adaptively choose erasure coding parameters and map data chunks to heterogeneous nodes under user-defined reliability requirements, plus two greedy algorithms for storage utilization and load balancing. Our dynamic schedulers store on average 45% more data items without significantly degrading I/O throughput compared to state-of-the-art algorithms.
Deadline-Aware Scheduling of Mixed-Criticality Tasks
ICPP 2025
HPC centers and cloud providers mix routine tasks with urgent real-time computations that must meet hard deadlines. Rather than reserving resources or killing lower-criticality tasks, we interleave critical and non-critical tasks. We formulate a bi-objective problem. Our goal is to guarantee all critical tasks meet their deadlines while minimizing the maximum flow of non-critical tasks. We prove an approximation algorithm as well as a lower bound, and develop several heuristics. Extensive simulations on synthetic and real-world workloads show one of our heuristic (in green on the figure) reduces the maximum flow of non-critical tasks by up to 14% compared to static resource partitioning.
PhD defense
My PhD defense took place on September 25th, 2023 at the LaBRI in Bordeaux, France. The title of the presentation was Scheduling Under Memory Constraint in Task-based Runtime Systems.
Abstract: Hardware accelerators, such as GPUs, now provide a large part of the computational power used for scientific simulations. GPUs come with their own limited memory and are connected to the main memory of the machine via a bus with limited bandwidth. Scientific simulations often operate on very large data, to the point of not fitting in the limited GPU memory. In this case, one has to turn to out-of-core computing, where data movement quickly becomes a performance bottleneck. During this thesis, we worked on the problem of scheduling for a task-based runtime to improve data locality in an out-of-core setting, in order to reduce data movements. We designed strategies for both task scheduling and data eviction from limited memories. We implemented them in the StarPU runtime and compared them to existing scheduling techniques. Our strategies achieves significantly better performance when scheduling tasks on multiple GPUs with limited memory, as well as on multiple CPU cores with limited main memory.
My PhD manuscrit is available here. A capture of my PhD defense is also available: